Loop statements in Verilog - forever,repeat,for and while

Loop statements are used for executing a block of statements repeatedly. If the block has more than one statement we can group them together under one loop using begin ... end keywords.

There are four loop statements in Verilog:

forever:

This type of looping is used to execute a block of statements forever, meaning until the end of simulation. Normally this is used for generating clock in a testbench. 

For example,

//The following block generates a Clock signal with 10*2=20 ns period 

//and 50 MHz frequency
initial 
begin 
   Clock = 0; 
   forever #10 Clock = ~Clock; 
end

repeat:

As the name suggests, this type of looping can be used to execute a block of statements repeatedly, for a fixed number of times. 

//Declare variables
    integer j=5;
    integer product;

//Code section for calculating product=4*j
//repeatedly add j, four times.
    initial 
    begin
        product = 0;
        repeat(4)
        begin
            product = product + j;
            $display("product = %d",product);
        end
    end

The following values will be printed in the console when you run the code:

product = 5
product = 10
product = 15

product = 20

for:

For loops are used, when you want to specify more conditions for the looping of the statements. Using a for loop, you can mention the starting value of a variable, the ending value of the variable and the step by which the value has to be incremented or decremented. It's similar to C or C++, except that you don't have ++ or -- operators.

    integer i;
    integer sum;
    //Add decimal numbers from 1 to 10
    initial 
    begin
        sum = 0; //initialize sum to zero.
        for(i = 1 ; i <= 10 ; i = i + 1)
        begin
            sum = sum + i;
        end 
        $display("sum = %d",sum); //display the sum in simulation console
        $finish; //stop the simulation.
    end

The following will be printed in the console when you run the code:
sum = 55

while:

While loop is used mostly in testbenches. The block of statements are repeatedly executed as long as the conditional expression is true.

Look at the example for the, for loop. I will implement the same logic using while loop here.

    //Add decimal numbers from 1 to 10
    initial 
    begin
        sum = 0; //initialize sum to zero.
        i = 1;
         //as long as i is less than or equal to 10,the block of statements are executed.
        while(i <= 10)
        begin
            sum = sum + i; //add i to sum
            i = i + 1; //increment i.
        end 
        $display("sum = %d",sum); //display the sum in simulation console
        $finish; //stop the simulation.
    end

The result will be the same,

sum = 55

Note:-

Its up to you, to decide which looping statement you want to use. But be careful with looping statements. Verilog is a Hardware Description Language(HDL) and most of the time ,the code you write has to be implemented in a real hardware. Large loops can cause excessive usage of resources, large delays and crazy synthesis times.