Verilog code for D Flip-Flop with Synchronous(and Asynchronous) Reset,Set and Clock Enable

In this post, I share the Verilog code for the most basic element in the synchronous domain - a D flip flop. There can be D flip flops with different functionalities whose behavior depends on how the flip flop is set or reset, how the clock affects the state of the flip flop, and the clock enable logic.

First we will implement a D flip flop with Synchronous Reset,Set and Clock Enable. The state of the flip flop is changed only on positive edge of the clock.

This code shows how a synchronous element is implemented in Verilog.

D flip flop with Synchronous Reset,Set and Clock Enable:

module DFF(
        Clk,
        CE,
        reset,
        D,
        set,
        Q
        );
        
//list the inputs 
    input Clk;
    input CE;
     input reset;
     input D;
     input set;
//list the outputs 
    output Q;
//Internal variables
     reg Q;
     
    //flip flop state is affected only on postive edge of clock 
    always @(posedge(Clk))
    begin
        if(Clk == 1) 
        begin
            if (reset == 1) //check for active high reset
                Q = 0;  
            else if(set == 1)   //check for set
             Q = 1; 
         else if (CE == 1) //check if clock is enabled
                 Q = D;       
      end      
    end 
    
endmodule

Testbench for D flip flop:

module tb_DFF;

    // Inputs
    reg Clk;
    reg CE;
    reg reset;
    reg D;
    reg set;

    // Outputs
    wire Q;

    // Instantiate the Unit Under Test (UUT)
    DFF uut (
        .Clk(Clk), 
        .CE(CE), 
        .reset(reset), 
        .D(D), 
        .set(set), 
        .Q(Q)
    );

//Clock generation with 100 MHz frequency.
    initial Clk = 0;
    always #10 Clk =~Clk;
    
    initial begin
        //Initialize inputs.
        CE = 0;
        reset = 0;
        D = 0;
        set = 0;
        #100;
        //Apply the inputs.
        D=1;
        reset = 1; #100;
        reset = 0; #100;
        set = 1; #100;
        set = 0; #100;
        CE = 1; #100;
        D = 0;  #100;
        CE = 0; #100;
        D = 1;  #100;
        set = 1; #100;
        set = 0; #100;
    end
      
endmodule

Simulation waveform:

The code, when correctly simulated will yield the following waveform in Xilinx ISE 13.1. Notice how the values of Q change only at the positive edge of Clk.

D flip flop with Asynchronous Reset,Set and Clock Enable:

In the second case we implement a D flip flop with asynchronous functions too. Lets go through the code here, to get a better understanding.

module DFF(
        Clk,
        CE,
        reset,
        D,
        set,
        Q
        );
        
//list the inputs 
    input Clk;
    input CE;
     input reset;
     input D;
     input set;
//list the outputs 
    output Q;
//Internal variables
     reg Q;
     
    //flip flop state is affected irrespective of the clock 
    always @(posedge(Clk) or posedge(reset) or posedge(set) or posedge(CE))
    begin
        if(reset == 1) //check for active high asynchronous reset
            Q = 0;
        else if(set == 1)   //check for asynchronous set
         Q = 1; 
      else if (Clk == 1 && CE == 1) //check if clock is enabled
            Q = D;             
    end 
    
endmodule

Note that we can use the same testbench used earlier for testing the second design. The waveform this time,would look a bit different:

You can see that this time the Q output is changed some times irrespective of the clock. The reset and set inputs have more priority than clock input, this time.