Verilog Coding Tips and Tricks: Concatenation Operator in Verilog

Tuesday, November 10, 2015

Concatenation Operator in Verilog

Concatenation is generally used for combining two or more vectors to form a single vector. But in Verilog, concatenation operator can be used to either join two or more vectors or split a vector into small sub-vectors.

{ and } together form the concatenation operator in Verilog.

I will show you some examples, to give you a practical idea.

Combing two or more vectors to form a single vector:

//Declare the registers
reg [7:0] c;  //8 bit vector
reg [4:0] a = 5'b11111;  //5 bit vector
reg [2:0] b = 3'b000;    //3 bit vector


//First way to concatenate
    c = {a,b};            // c = "11111000"                       
    c = {b,a};            // c = "00011111"
    
//Replicate a vector multiple times by using {{}}   
// {a{b}} means 'b' replicated 'a' times.

// size of "1" is not mentioned. so its taken as a 32 bit integer.
    c = {{1}};           // c = "00000001"

// size of "1" is mentioned and its replicated 8 times. 
    c = {8{1'b1}};       // c = "11111111"
    
//the replicated part will be added to Least significant bits. MSB is padded with zeros.    
    c = {4{1'b1}};       // c = "00001111"
   
//Note that MSB is padded with zeros again  
    c = {{2'b10}};       // c = "00000010"

//"10" is replicated 4 times.   
    c = {4{2'b10}};       // c = "10101010"  

//replicate "110" eight times and take the least significant 8 bits.    
    c = {8{3'b110}};      // c = "10110110"

// Compilation error. Multiple concatenating is not allowed.
    c = {2{4{1'b1}}};     

Splitting a vector to smaller vectors:

//Declare variables
reg [7:0] e = 8'b10110110;  //8 bit vector
reg [4:0] d;  //5 bit vector
reg [2:0] a,b,c;    //3 bit vector

//splitting up a vector to two vectors. 
    {a,d} = e;               // a = "101" and d = "10110"   

//splitting up a vector to three vectors.   
//Least significant vectors(right hand side) is filled first.
// remaining vectors are assigned zero.
    {a,b,c} = 8'b11111111;   // a = "011" , b = "111" , c = "111"

//splitting up a vector to three vectors.   
//10 times "10" is replicated.  
    {a,b,c} = {10{2'b10}};   // a = "010" , b = "101" , c = "010"

I hope the concept of concatenation operator is clear now. A clear understanding of this might save you, lots of typing, when you are implementing your Verilog design.

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