Module Instantiation methods in Verilog

Every digital design is implemented in Verilog using one or more modules, depending on the size of the design. Once designed, you can think a module as a black box of defined inputs and outputs. How the outputs are derived from inputs, isn't our concern any more. We are concerned only with the functionality of the module.

These smaller modules(or black boxes) can be used to build bigger modules. To use a Verilog module in another one, we have to use Instantiation. By Instantiating we tell the compiler that, how the signals in the bigger module are connected to the smaller(instantiated) module.

There are many ways to achieve this.

Let's say we have a module which looks like this:

module arith(
    A,
    B,
    C,
    D,
    Sum,
    Product
    );

Method 1 : Named Association

    arith uut1 (
        .A(A_in_topmodule), 
        .B(B_in_topmodule), 
        .C(C_in_topmodule),
        .D(D_in_topmodule),
        .Sum(Sum_in_topmodule),
        .Product(Product_in_topmodule)
    );

This is the most common way of instantiating a module. We mention the port names of the instantiated module and the signal names in the top module to which they are connected.

This method is the safest, because there is low chance that we might connect the wrong signals to the ports. Plus, its easy to understand for another programmer, going through the code.

In case you don't want to use some of the ports, we can still use this method.

    arith uut1 (
        .A(A_in_topmodule), 
        .B(B_in_topmodule), 
        .C(),    
        .D(),
        .Sum(Sum_in_topmodule),
        .Product()
    );

Empty parentheses means no signal is connected to that particular port. 

Method 2 : Positional Association

    arith uut1 (
        A_in_topmodule,
        B_in_topmodule,
        C_in_topmodule,
        D_in_topmodule,
        Sum_in_topmodule,
        Product_in_topmodule
        );

This method is a short cut way of instantiating. As the name suggests, the signals in the top modules are connected in the same order as the ports are declared in the instantiated module.

Even though it makes the job easier at the time of coding, it might cost you some time later on. For a second person going through the code, it will take him/her much more time to understand. Plus there is more chance that we might connect the wrong signal to the wrong ports.

In case you don't want to use some of the ports,

    arith uut1 (
        A_in_topmodule,
        B_in_topmodule,
        ,
        ,
        Sum_in_topmodule,
        
        );

Just keep the commas. You really don't need to leave an empty line as shown above. I did it so that, it's more easy for you to understand.

Method 3 : Mixing Implicit naming and Named Association

    arith uut1 (
        .A,
        .B,
        .C,
        .D,
        .Sum(Sum_in_topmodule),
        .Product(Product_in_topmodule)
        );

Suppose some of the signals have the same name as the ports and some of them are different. In the above instantiation, we can see that the first four signals have the same name and so we didn't mention any signal names inside parentheses. For the last two ports, the signal names are different from the port names and so they are mentioned inside the parentheses.

It's up to you, to decide which method to use to instantiate a module. I normally go with named association method. 

So, what's your favorite method of instantiation?