Verilog code for Carry Look Ahead adder with Testbench

The simplest form of adder is Ripple carry adder. But sometimes we might need adders which are faster than that. That is when Carry look ahead adders come to the rescue.

By calculating all the carry's in advance, this type of adder achieves lower propagation delays and thus higher performance. The disadvantage comes from the fact that, as the size of inputs goes beyond 4 bits, the adder becomes much more complex.

In this post I have written a Verilog code for a 4 bit carry look ahead adder. For the block diagram and explanation of the logic, you might want to see pages 1 to 3 in this pdf.

cla_adder.v

module cla_adder
        (   input [3:0] A,B,
            input cin,
            output [3:0] S,
            output cout
            );
            
wire [3:0] P,G;
wire [4:0] C;   
    
//first level
assign P = A ^ B;
assign G = A & B;

//second level
cla_block gen_c(P,G,cin,C);

//third level
assign S = P ^ C[3:0];
assign cout = C[4];

endmodule

cla_block.v

module cla_block
        (   input [3:0] P,G,
            input cin,
            output [4:0] C
            );
            
assign C[0] = cin;
assign C[1] = G[0] | (P[0] & cin);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & cin);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & cin);
assign C[4] = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | 
            (P[3] & P[2] & P[1] & G[0]) | (P[3] & P[2] & P[1] & P[0] & cin);

endmodule

Testbench code:

I have used the same testbench code(tb_adder.vhd), at the bottom of this post. But make sure you change the name of the initiated entity.

Simulated waveform:

The design was synthesised and simulated using Xilinx ISE 14.6.

The waveform should look like this. The code checks for all the input combinations and the signal "error" shows the number of errors. If all goes well, "error" signal should remain at zero.