Structural Level Coding with Verilog using MUX example

A multiplexer (or mux) is a device that selects one of several input signals and forwards the selected input into a single output line. In some previous posts, I have shared the Verilog code for 2:1 MUX's using Behavioral modelling and Gate level modelling. You might have to use either of these codes in this example.

In this post, I demonstrate structural level coding using Verilog. I use the 2:1 MUX's to create a 4:1 MUX. A 4:1 MUX has 4 input bits, a 2 bit select signal and one single output bit. It can be implemented using three 2:1 MUX's as shown below:

       

Image from here.

4:1 MUX Structural level Design:

//Declare the ports of the module
module mux4to1(
    Data_in_0,
    Data_in_1,
    Data_in_2,
    Data_in_3,
    sel,
    Data_out
    );

//list the inputs and their sizes
    input Data_in_0;
    input Data_in_1;
    input Data_in_2;
    input Data_in_3;
    input [1:0] sel;
//list the outputs and their sizes  
    output Data_out;
    
//Instantiate the mux for selecting between input 0 or 1.   
    mux2to1 low_mux (
        .Data_in_0(Data_in_0), 
        .Data_in_1(Data_in_1), 
        .sel(sel[0]),   //LSB of sel is connected here
        .Data_out(Data_temp1)
    );

//Instantiate the mux for selecting between input 2 or 3.       
    mux2to1 high_mux (
        .Data_in_0(Data_in_2), 
        .Data_in_1(Data_in_3), 
        .sel(sel[0]),   //LSB of sel is connected here
        .Data_out(Data_temp2)
    );
    
//Instantiate the mux for selecting between low or high mux output  
    mux2to1 last_mux (
        .Data_in_0(Data_temp1), 
        .Data_in_1(Data_temp2), 
        .sel(sel[1]),   //MSB of sel is connected here
        .Data_out(Data_out)  //The output of module is connected here.
    );
    
endmodule

Testbench for 4:1 MUX

module tb_tm;

    // Inputs
    reg Data_in_0;
    reg Data_in_1;
    reg Data_in_2;
    reg Data_in_3;
    reg [1:0] sel;

    // Outputs
    wire Data_out;

    // Instantiate the Unit Under Test (UUT)
    mux4to1 uut (
        .Data_in_0(Data_in_0), 
        .Data_in_1(Data_in_1), 
        .Data_in_2(Data_in_2), 
        .Data_in_3(Data_in_3), 
        .sel(sel), 
        .Data_out(Data_out)
    );

    initial begin
        // Initialize Inputs
        Data_in_0 = 0;
        Data_in_1 = 0;
        Data_in_2 = 0;
        Data_in_3 = 0;
        sel = 0;    
        #100;
        Data_in_0 = 1;  #100;
        Data_in_0 = 0;  Data_in_1 = 1;  #100;   sel = 1;    #100;
        Data_in_1 = 0;  Data_in_2 = 1;  #100;   sel = 2;    #100;
        Data_in_2 = 0;  Data_in_3 = 1;  #100;   sel = 3;    #100;
    end
      
endmodule

Simulation waveform:

I used Xilinx ISE 13.1 for simulation.