Hi I am Vipin, the author behind this blog. This blog is what I learned in Verilog through my experience. I consider myself, still as a newbie in Verilog and forgive me if you find any mistakes in my posts.
My primary blog, VHDLGURU runs here on http://vhdlguru.blogspot.com/.
I have another blog where I write about embedded systems, FPGA's and other digital technology fundamentals.The blog can be accessed here.
My primary blog, VHDLGURU runs here on http://vhdlguru.blogspot.com/.
I have another blog where I write about embedded systems, FPGA's and other digital technology fundamentals.The blog can be accessed here.
Hello, Sir.
ReplyDeleteI am posting this comment as a question. I want to create a system that compares the user's input data with a pre-existing bit sequence in the machine. Essentially, if the pre-existing sequence is 11011, and the user types 1, and then 1, and then 0, and then 0, I want the machine to show an error because the last bit that the user entered , i.e. 0, was not in the sequence which is 11011. How can I implement this functionality in my system?
I would really appreciate your help in this case and and your guidance on how to solve this problem. Thank you very much.
Sincerely,
Harsimrat.