Generic Verilog Code for Binary to Gray and Gray to Binary converter

     Few years back I had written a 4 bit converter for conversion between Gray and Binary codes. After receiving much positive response I decided to write a generic version of the same.

Let me share the codes...

Binary to Gray Code Converter:

//Binary to Gray code Converter

//The 'parameter' keyword below is how we give the inputs/outputs a generic size.

module bin2gray #(parameter N = 4)

        ( input [N-1:0] bin,    //binary input

        output [N-1:0] G);      //Gray output

assign G[N-1] = bin[N-1];

//generate xor gates.

//the loop index need to be declared as 'genvar' and it can be done

//as you can see inside the 'for' loop.

//The instantiation is labelled as 'xor_gates_b2g'. 

//Always put a label when you generate instantiations.

//The 'generate' keyword need not be explicitly written.

for(genvar i=N-2;i>=0;i=i-1) begin : xor_gates_b2g

    xor(G[i],bin[i+1],bin[i]);

end

endmodule

Gray Code to Binary Converter:

//Gray code to Binary Converter

module gray2bin #(parameter N = 4)

        ( input [N-1:0] G,    //Gray input

        output [N-1:0] bin);      //Binary output

assign bin[N-1] = G[N-1];

for(genvar i=N-2;i>=0;i=i-1) begin : xor_gates_g2b

    xor(bin[i],G[i],bin[i+1]);

end

endmodule

Testbench:

//Testbench which connects both the converters back to back.

module tb;  //testbench module is always empty.

parameter N = 16;   //Change this to control the number of bits in the input/output.

reg [N-1:0] bin;

wire [N-1:0] G,bin_out;

reg [N:0] i;

integer error;  //this counts the number of errors during simulation.

    //Both the converters are connected back to back to see the binary input going to the

    //first module is the same as the output coming out of the second module.

    bin2gray #(.N(N)) uut1

        (

          .bin(bin),

          .G(G)

        );

 

    gray2bin #(.N(N)) uut2

        (

          .G(G),  

          .bin(bin_out)

        );

          

    initial 

    begin

        error = 0;  //initialize the error as zero.

        for(i=0;i<2**N;i=i+1) begin     //loop through all the  available inputs 

            bin = i[N-1:0];

            #5;

            //Count the number of errors.It should be zero at the end of simulation.

            if(bin != bin_out)  

                error = error + 1;

            #5;

        end

        #10;

        $stop;  //All possible inputs are tested. So stop the simulation.

    end          

endmodule

    The codes were tested using Modelsim 10.4a version. Simply change the value of the parameter 'N' in the testbench to test for different sized converters.

A screenshot of the simulation waveform is shown below:

4 bit Binary to Gray code and Gray code to Binary converter in Verilog

UPDATE : A GENERIC GRAY CODE CONVERTER IS AVAILABLE HERE

Gray codes are non-weighted codes, where two successive values differ only on one bit. Through this post, I want to share two simple gate level Verilog codes for converting binary number to Gray and vice versa.

Logic circuit for 4 bit Binary to Gray code converter:

Logic circuit for 4 bit Gray code to Binary converter:

Verilog Code for Binary to Gray code conversion:

module bin2gray
        (input [3:0] bin, //binary input
         output [3:0] G //gray code output
        );

//xor gates.
assign G[3] = bin[3];
assign G[2] = bin[3] ^ bin[2];
assign G[1] = bin[2] ^ bin[1];
assign G[0] = bin[1] ^ bin[0];

endmodule

Verilog Code for Gray code to Binary conversion:

module gray2bin
        (input [3:0] G, //gray code output
         output [3:0] bin   //binary input
        );

assign bin[3] = G[3];
assign bin[2] = G[3] ^ G[2];
assign bin[1] = G[3] ^ G[2] ^ G[1];
assign bin[0] = G[3] ^ G[2] ^ G[1] ^ G[0];

endmodule

Single Testbench for both the designs:

module tb();

   reg [3:0] bin;
    wire [3:0] G,bin_out;
    
    // instantiate the unit under test's (uut)
   bin2gray uut1(bin,G);
   gray2bin uut2(G,bin_out);
    
   // stimulus
   always
   begin        
      bin <= 0; #10;
        bin <= 1;   #10;
        bin <= 2;   #10;
        bin <= 3;   #10;
        bin <= 4;   #10;
        bin <= 5;   #10;
        bin <= 6;   #10;
        bin <= 7;   #10;
        bin <= 8;   #10;
        bin <= 9;   #10;
        bin <= 10;  #10;
        bin <= 11;  #10;
        bin <= 12;  #10;
        bin <= 13;  #10;
        bin <= 14;  #10;
        bin <= 15;  #10;
        #100;   
      $stop;
   end

endmodule

Simulation Waveform:

The code was simulated using Xilinx ISE 14.6 tool. The following waveform verifies the correctness of both the designs. The output of binary to gray module is connected as input of gray to binary converter. As you can see the bin and bin_out signals are the same. This verifies that the codes are working well.

Do you notice a pattern in how the output bits are calculated. What do you think of of an n-bit converter? For learning purposes, try implementing an n-bit version of the above designs.

I have also implemented the exact logic circuit in VHDL. If interested visit it in my VHDLblog, 4 bit VHDL code for gray code to binary and vice versa.