Structural Level Coding with Verilog using MUX example

A multiplexer (or mux) is a device that selects one of several input signals and forwards the selected input into a single output line. In some previous posts, I have shared the Verilog code for 2:1 MUX's using Behavioral modelling and Gate level modelling. You might have to use either of these codes in this example.

In this post, I demonstrate structural level coding using Verilog. I use the 2:1 MUX's to create a 4:1 MUX. A 4:1 MUX has 4 input bits, a 2 bit select signal and one single output bit. It can be implemented using three 2:1 MUX's as shown below:

       

Image from here.

4:1 MUX Structural level Design:

//Declare the ports of the module
module mux4to1(
    Data_in_0,
    Data_in_1,
    Data_in_2,
    Data_in_3,
    sel,
    Data_out
    );

//list the inputs and their sizes
    input Data_in_0;
    input Data_in_1;
    input Data_in_2;
    input Data_in_3;
    input [1:0] sel;
//list the outputs and their sizes  
    output Data_out;
    
//Instantiate the mux for selecting between input 0 or 1.   
    mux2to1 low_mux (
        .Data_in_0(Data_in_0), 
        .Data_in_1(Data_in_1), 
        .sel(sel[0]),   //LSB of sel is connected here
        .Data_out(Data_temp1)
    );

//Instantiate the mux for selecting between input 2 or 3.       
    mux2to1 high_mux (
        .Data_in_0(Data_in_2), 
        .Data_in_1(Data_in_3), 
        .sel(sel[0]),   //LSB of sel is connected here
        .Data_out(Data_temp2)
    );
    
//Instantiate the mux for selecting between low or high mux output  
    mux2to1 last_mux (
        .Data_in_0(Data_temp1), 
        .Data_in_1(Data_temp2), 
        .sel(sel[1]),   //MSB of sel is connected here
        .Data_out(Data_out)  //The output of module is connected here.
    );
    
endmodule

Testbench for 4:1 MUX

module tb_tm;

    // Inputs
    reg Data_in_0;
    reg Data_in_1;
    reg Data_in_2;
    reg Data_in_3;
    reg [1:0] sel;

    // Outputs
    wire Data_out;

    // Instantiate the Unit Under Test (UUT)
    mux4to1 uut (
        .Data_in_0(Data_in_0), 
        .Data_in_1(Data_in_1), 
        .Data_in_2(Data_in_2), 
        .Data_in_3(Data_in_3), 
        .sel(sel), 
        .Data_out(Data_out)
    );

    initial begin
        // Initialize Inputs
        Data_in_0 = 0;
        Data_in_1 = 0;
        Data_in_2 = 0;
        Data_in_3 = 0;
        sel = 0;    
        #100;
        Data_in_0 = 1;  #100;
        Data_in_0 = 0;  Data_in_1 = 1;  #100;   sel = 1;    #100;
        Data_in_1 = 0;  Data_in_2 = 1;  #100;   sel = 2;    #100;
        Data_in_2 = 0;  Data_in_3 = 1;  #100;   sel = 3;    #100;
    end
      
endmodule

Simulation waveform:

I used Xilinx ISE 13.1 for simulation. 

Verilog code for 2:1 MUX using Gate level modelling

In a previous article I posted the Verilog code for 2:1 MUX using behavioral level coding. In this post I have shared the code for the same 2:1 MUX with a gate level approach.

A 2:1 MUX is simple combinational circuit which follows the following Inputs-Output relationship:



Where,
Z is the output.
A and B are data inputs.
S is the select signal.

To create the circuit, I have used built in primitive logic gates in Verilog. The gates have one output and multiple inputs. The first signal is the output and the remaining ones are inputs.

2:1 MUX with Gate level modelling:

//declare the Verilog module - The inputs and output signals.
module mux2to1(
    Data_in_0,
    Data_in_1,
    sel,
    Data_out
    );

    //what are the input ports.
    input Data_in_0;
    input Data_in_1;
    input sel;
    //What are the output ports.
    output Data_out;
    //Internal variables.
    wire not_sel;
    wire temp1,temp2;
    wire Data_out_temp;

    //NOT gate - first signal(not_sel) is output and others are inputs.
    not n1(not_sel,sel);  
    //AND   gate - first signal(temp1 and temp2) is output and others are inputs.
    and and_1(temp1,Data_in_0,not_sel);
    and and_2(temp2,Data_in_1,sel);
    //OR gate - first signal(Data_out_temp) is output and others are inputs.
    or or_1(Data_out_temp,temp1,temp2);
    
    //Assign the final value to the output port.
    assign Data_out = Data_out_temp;
    
endmodule

To simulate this code you can use the same testbench code available in this post. The simulated waveform is also available here.

Verilog Code for 2:1 MUX using if statements

This post is for Verilog beginners. 2:1 MUX is a very simple digital block with 2 data inputs, one select input and one data output.

The code follows Behavioral modelling. There are many ways you can write a code for 2:1 mux. I have used simple 'if .. else ..' statement here.

2:1 MUX:

//declare the Verilog module - The inputs and output signals.
module mux2to1(
    Data_in_0,
    Data_in_1,
    sel,
    Data_out
    );

    //what are the input ports.
    input Data_in_0;
    input Data_in_1;
    input sel;
    //What are the output ports.
    output Data_out;
    //Internal variables.
    reg Data_out;

    //Always block - the statements inside this block are executed when the given sensitivity list 
    //is satidfied. for example in this case the block is executed when any changes occur in the three signals 
    //named 'Data_in_0','Data_in_1' or 'sel'.
    always @(Data_in_0,Data_in_1,sel)
    begin
        if(sel == 0) 
            Data_out = Data_in_0;  //when select signal to the mux is low
        else
            Data_out = Data_in_1;  //when select signal to the mux is high
    end
    
endmodule


Testbench for 2:1 MUX:

module tb_mux;

    // Declaring Inputs
    reg Data_in_0;
    reg Data_in_1;
    reg sel;

    // Declaring Outputs
    wire Data_out;

    // Instantiate the Unit Under Test (UUT)
    mux2to1 uut (
        .Data_in_0(Data_in_0), 
        .Data_in_1(Data_in_1), 
        .sel(sel), 
        .Data_out(Data_out)
    );

    initial begin
        // Apply Inputs
        Data_in_0 = 0;
        Data_in_1 = 0;
        sel = 0;
        // Wait 100 ns
        #100;
        
        //Similarly apply Inputs and wait for 100 ns
        Data_in_0 = 0;      Data_in_1 = 0;      sel = 1;      #100;
        Data_in_0 = 0;      Data_in_1 = 1;      sel = 0;      #100;
        Data_in_0 = 0;      Data_in_1 = 1;      sel = 1;      #100;
        Data_in_0 = 1;      Data_in_1 = 0;      sel = 0;      #100;
        Data_in_0 = 1;      Data_in_1 = 0;      sel = 1;      #100;
        Data_in_0 = 1;      Data_in_1 = 1;      sel = 0;      #100;
        Data_in_0 = 1;      Data_in_1 = 1;      sel = 1;      #100;
    end
      
endmodule

Simulation waveform:

When the codes are correctly simulated you should be able to get the following waveform:

The code was tested on Xilinx ISE 13.1. But it should work on almost all compilers and simulators.