Verilog Coding Tips and Tricks: How to Simulate your Verilog codes Online?

Tuesday, November 17, 2015

How to Simulate your Verilog codes Online?

Have you wondered how useful it would be to have an online Verilog compiler and simulator? How useful it would be to just copy and paste the code to a web simulator and verify the design without going through all the detailed steps in your computer? Then you are lucky!

EdaPlayground developed by Duolos is the answer. This web service allows you to test your Verilog,System Verilog or Python codes online for free. You can log in to the service with a Google or Facebook account and start compiling and simulating your design. 

The service also allows you to save your designs for later reference and lets you share them with a simple link. 

There is an option to see the simulation waveform too. But for this you have to add the following two lines in your testbench "initial" statement.

    $dumpvars(1, test);   //replace test with the testbench module name

One more useful feature worth mentioning is the Collaborate option. This lets you share the design workspace with a fellow coder so that you can learn from each other. You can chat with your friend and create the design together. But note that the feature is still in beta mode.

I wouldn't explain here how to use this web service in depth. Because they have explained it well, through this Youtube video.

Happy Designing!!!

1 comment:

  1. i hve wrote $dumpfile n $dumpvars ,but it is throughing syntax error