In this post, I want to share the Verilog code for a JK flip flop with synchronous reset,set and clock enable. The particular flip flop I want to talk about is designed by Xilinx and is called by the name, FJKRSE.
The truth table for FJKRSE:
From the truth table, we can see that reset(R) has the highest priority and set(S) the next priority, then the clock enable (CE) and then the J or K inputs.
JK flip flop:
//JK flip flop module
module FJKRSE(J,K,Clk,R,S,CE,Qout);
input J,K; //inputs
input Clk; //Clock
input R; //synchronous reset (R)
input S; //synchronous set (S)
input CE; //clock enable (CE)
output Qout; //data output (Q)
//Internal variable
reg Qout;
always@ (posedge(Clk)) //Everything is synchronous to positive edge of clock
begin
if(R == 1) //reset has highest priority.
Qout = 0;
else
if(S == 1) //set has next priority
Qout = 1;
else
if(CE == 1) //J,K values are considered only when CE is ON.
if(J == 0 && K == 0)
Qout = Qout; //no change
else if(J == 0 && K == 1)
Qout = 0; //reset
else if(J == 1 && K == 0)
Qout = 1; //set
else
Qout = ~Qout; //toggle
else
Qout = Qout; //no change
end
endmodule
module FJKRSE(J,K,Clk,R,S,CE,Qout);
input J,K; //inputs
input Clk; //Clock
input R; //synchronous reset (R)
input S; //synchronous set (S)
input CE; //clock enable (CE)
output Qout; //data output (Q)
//Internal variable
reg Qout;
always@ (posedge(Clk)) //Everything is synchronous to positive edge of clock
begin
if(R == 1) //reset has highest priority.
Qout = 0;
else
if(S == 1) //set has next priority
Qout = 1;
else
if(CE == 1) //J,K values are considered only when CE is ON.
if(J == 0 && K == 0)
Qout = Qout; //no change
else if(J == 0 && K == 1)
Qout = 0; //reset
else if(J == 1 && K == 0)
Qout = 1; //set
else
Qout = ~Qout; //toggle
else
Qout = Qout; //no change
end
endmodule
Testbench for JK flip flop:
module tb_jkff;
// Inputs
reg J;
reg K;
reg Clk;
reg R;
reg S;
reg CE;
// Outputs
wire Qout;
// Instantiate the Unit Under Test (UUT)
FJKRSE uut (
.J(J),
.K(K),
.Clk(Clk),
.R(R),
.S(S),
.CE(CE),
.Qout(Qout)
);
//Create 50 Mhz clock(20 ns clock period).
initial Clk = 0;
always #10 Clk = ~Clk;
initial begin
// Initialize Inputs
J = 0;
K = 0;
R = 0;
S = 0;
CE = 0;
#30;
//Apply inputs
R = 1; #50;
R = 0;
S = 1; #50;
S = 0;
J = 1; K = 1; #50;
CE = 1; #50;
J = 0; K = 0; #50;
J = 0; K = 1; #50;
J = 1; K = 0; #50;
J = 1; K = 1; #50;
CE = 0;
end
endmodule
// Inputs
reg J;
reg K;
reg Clk;
reg R;
reg S;
reg CE;
// Outputs
wire Qout;
// Instantiate the Unit Under Test (UUT)
FJKRSE uut (
.J(J),
.K(K),
.Clk(Clk),
.R(R),
.S(S),
.CE(CE),
.Qout(Qout)
);
//Create 50 Mhz clock(20 ns clock period).
initial Clk = 0;
always #10 Clk = ~Clk;
initial begin
// Initialize Inputs
J = 0;
K = 0;
R = 0;
S = 0;
CE = 0;
#30;
//Apply inputs
R = 1; #50;
R = 0;
S = 1; #50;
S = 0;
J = 1; K = 1; #50;
CE = 1; #50;
J = 0; K = 0; #50;
J = 0; K = 1; #50;
J = 1; K = 0; #50;
J = 1; K = 1; #50;
CE = 0;
end
endmodule
Simulation Waveform:
The codes were simulated in Xilinx ISE 13.1 and we got the following waveform.
Note how the outputs are changed only at the positive edge of the clock. Also note how the priority of reset,set and clock enable works,
No comments:
Post a Comment