BCD or Binary coded decimal is a way of representing decimal digits in binary form. Generally 4 bits are used to represent values 0 to 9.
In this post, I want to discuss about, how two BCD digits can be added. Later, I write the code in Verilog, implementing a basic BCD adder.
Consider the below BCD addition :
The output 17 is more than 9. So we add 6 to it. So we get,
For multiple digit addition , you can connect the carry_out to the carry input of the next adder. A simple cascading network of these small adders is enough to realize the multiple digit BCD addition. I suggest you try to implement a 4 digit BCD adder as homework, using the below module.
Decimal Digit | BCD 8 4 2 1 |
---|---|
0 | 0 0 0 0 |
1 | 0 0 0 1 |
2 | 0 0 1 0 |
3 | 0 0 1 1 |
4 | 0 1 0 0 |
5 | 0 1 0 1 |
6 | 0 1 1 0 |
7 | 0 1 1 1 |
8 | 1 0 0 0 |
9 | 1 0 0 1 |
In this post, I want to discuss about, how two BCD digits can be added. Later, I write the code in Verilog, implementing a basic BCD adder.
A BCD adder, takes in two BCD numbers as inputs, and outputs a BCD digit along with a carry output. If the sum of the BCD digits is less than or equal to 9, then we don't have a problem. But if its greater than 9, we have to convert it into BCD format. This is done by adding 6 to the sum and taking only the least significant 4 bits. The MSB bit is output as carry.
Consider the below BCD addition :
1001 + 1000 = 10001 9 + 8 = 17
17+6 = 23 (in binary 23 is 10111)
Now the least significant 4 bits(which is "0111") represent the units digit and the MSB(4th bit which is '1') bit represents the tens digit.
Since the range of input is 0 to 9, the maximum output is 18. If you consider a carry it becomes 19. This means at the output side we need a 4 bit sum and a 1 bit carry to represent the most significant digit.
For multiple digit addition , you can connect the carry_out to the carry input of the next adder. A simple cascading network of these small adders is enough to realize the multiple digit BCD addition. I suggest you try to implement a 4 digit BCD adder as homework, using the below module.
Verilog code for BCD addition:
//module declaration with inputs and outputs
module bcd_adder(a,b,carry_in,sum,carry);
//declare the inputs and outputs of the module with their sizes.
input [3:0] a,b;
input carry_in;
output [3:0] sum;
output carry;
//Internal variables
reg [4:0] sum_temp;
reg [3:0] sum;
reg carry;
//always block for doing the addition
always @(a,b,carry_in)
begin
sum_temp = a+b+carry_in; //add all the inputs
if(sum_temp > 9) begin
sum_temp = sum_temp+6; //add 6, if result is more than 9.
carry = 1; //set the carry output
sum = sum_temp[3:0]; end
else begin
carry = 0;
sum = sum_temp[3:0];
end
end
endmodule
module bcd_adder(a,b,carry_in,sum,carry);
//declare the inputs and outputs of the module with their sizes.
input [3:0] a,b;
input carry_in;
output [3:0] sum;
output carry;
//Internal variables
reg [4:0] sum_temp;
reg [3:0] sum;
reg carry;
//always block for doing the addition
always @(a,b,carry_in)
begin
sum_temp = a+b+carry_in; //add all the inputs
if(sum_temp > 9) begin
sum_temp = sum_temp+6; //add 6, if result is more than 9.
carry = 1; //set the carry output
sum = sum_temp[3:0]; end
else begin
carry = 0;
sum = sum_temp[3:0];
end
end
endmodule
Testbench for BCD adder:
module tb_bcdadder;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg carry_in;
// Outputs
wire [3:0] sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
bcd_adder uut (
.a(a),
.b(b),
.carry_in(carry_in),
.sum(sum),
.carry(carry)
);
initial begin
// Apply Inputs
a = 0; b = 0; carry_in = 0; #100;
a = 6; b = 9; carry_in = 0; #100;
a = 3; b = 3; carry_in = 1; #100;
a = 4; b = 5; carry_in = 0; #100;
a = 8; b = 2; carry_in = 0; #100;
a = 9; b = 9; carry_in = 1; #100;
end
endmodule
// Inputs
reg [3:0] a;
reg [3:0] b;
reg carry_in;
// Outputs
wire [3:0] sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
bcd_adder uut (
.a(a),
.b(b),
.carry_in(carry_in),
.sum(sum),
.carry(carry)
);
initial begin
// Apply Inputs
a = 0; b = 0; carry_in = 0; #100;
a = 6; b = 9; carry_in = 0; #100;
a = 3; b = 3; carry_in = 1; #100;
a = 4; b = 5; carry_in = 0; #100;
a = 8; b = 2; carry_in = 0; #100;
a = 9; b = 9; carry_in = 1; #100;
end
endmodule
Simulation waveform:
When the codes are simulated in Xilinx ISE 13.1, you should get the above waveform.
4 bit bcd adder code i need urgent pls send me on this mailid:mohammedabdullah2662@gmail.com
ReplyDeletedid you got
Delete# ERROR: bcdn.v(15): near ",": expecting: ')' OR
ReplyDelete# ERROR: C:/Modeltech_5.4a/win32/vlog failed.
# Error in macro ./bcd_adder.ldo line 4
How to do this using continuous assignment "assign"?
ReplyDeletehow i want to make the carry out be the carry in for next adder
ReplyDelete4 digit bcd adder code needed urgent
ReplyDelete