A seven-segment display (SSD) is a form of electronic display device for displaying decimal numbers. They can be used as an alternative to complex display's such as dot matrix.
A SSD has 7 segments and theoretically we can use it to display 2^7 = 128 combinations of characters. But most of these combinations, doesn't make sense to a human eye. Decimal numbers can be displayed correctly on a 7 segment panel as shown below:
The image on the right indicates the order in which the panels are accessed normally. This is done using a 7 bit vector.
Here, I have written a Verilog code which takes in a BCD number and converts it into a 6 bit vector format, which the seven segment panel understands. Note that, to light up an individual panel, we have to switch it OFF(pass '0' through it).
Seven segment display Code:
//Verilog module.
module segment7(
bcd,
seg
);
//Declare inputs,outputs and internal variables.
input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
//always block for converting bcd digit into 7 segment format
always @(bcd)
begin
case (bcd) //case statement
0 : seg = 7'b0000001;
1 : seg = 7'b1001111;
2 : seg = 7'b0010010;
3 : seg = 7'b0000110;
4 : seg = 7'b1001100;
5 : seg = 7'b0100100;
6 : seg = 7'b0100000;
7 : seg = 7'b0001111;
8 : seg = 7'b0000000;
9 : seg = 7'b0000100;
//switch off 7 segment character when the bcd digit is not a decimal number.
default : seg = 7'b1111111;
endcase
end
endmodule
module segment7(
bcd,
seg
);
//Declare inputs,outputs and internal variables.
input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
//always block for converting bcd digit into 7 segment format
always @(bcd)
begin
case (bcd) //case statement
0 : seg = 7'b0000001;
1 : seg = 7'b1001111;
2 : seg = 7'b0010010;
3 : seg = 7'b0000110;
4 : seg = 7'b1001100;
5 : seg = 7'b0100100;
6 : seg = 7'b0100000;
7 : seg = 7'b0001111;
8 : seg = 7'b0000000;
9 : seg = 7'b0000100;
//switch off 7 segment character when the bcd digit is not a decimal number.
default : seg = 7'b1111111;
endcase
end
endmodule
Testbench:
module tb_segment7;
reg [3:0] bcd;
wire [6:0] seg;
integer i;
// Instantiate the Unit Under Test (UUT)
segment7 uut (
.bcd(bcd),
.seg(seg)
);
//Apply inputs
initial begin
for(i = 0;i < 16;i = i+1) //run loop for 0 to 15.
begin
bcd = i;
#10; //wait for 10 ns
end
end
endmodule
reg [3:0] bcd;
wire [6:0] seg;
integer i;
// Instantiate the Unit Under Test (UUT)
segment7 uut (
.bcd(bcd),
.seg(seg)
);
//Apply inputs
initial begin
for(i = 0;i < 16;i = i+1) //run loop for 0 to 15.
begin
bcd = i;
#10; //wait for 10 ns
end
end
endmodule
Simulation Waveform:
The codes were correctly simulated in Xilinx ISE 13.1. Check the waveform below:
need help
ReplyDeleteHi, Im having a really odd error where there appears to be a ghost number when 5 or 6 are selected but not with any other number
ReplyDeletehow to create coding for displaying character in seven segments
ReplyDeletefrom the above same program include a to f numbers by using 0 and 1.
DeleteUsing two seven segment how to display from 0 to 20 numbers in fpga
ReplyDeletehow to make it count till giving number like 30 ?
ReplyDeletewhy in simulation i value goes up to 31
ReplyDeleteTo show multiple digits on display, use this code ( https://verilogcodes.blogspot.com/2015/10/verilog-code-for-8-bit-binary-to-bcd.html ) to convert binary number into multiple BCD digits and then use the code in this post on each BCD digit.
ReplyDelete