Verilog Coding Tips and Tricks: Verilog code for 8 bit Binary to BCD using Double Dabble algorithm

Monday, October 26, 2015

Verilog code for 8 bit Binary to BCD using Double Dabble algorithm

BCD or Binary-coded decimal is a class of binary encodings of decimal numbers where each decimal digit is represented by four bits. This format is useful for displaying a value in a seven segment display or LCD panel. 

To convert a binary number to BCD format, we can use an algorithm called Double Dabble. In this post I have written a Verilog code for converting a 8 bit binary number into BCD format. The maximum value of a 8 bit binary number is 255 in decimal. This means we need 3 BCD digits in the output. So I have chosen the size of the output as 3 digits*4 bits = 12 bits.

Note that I am not using a clock in this module. Everything is combinational. As the binary input gets bigger in size, this might use up a lot of resources and will result in more combinational path delay. I suggest as a home work, try to re-write the below code by adding a Clock to the module.

Binary to BCD converter:

module bin2bcd(
    bin,
     bcd
    );

    
    //input ports and their sizes
    input [7:0] bin;
    //output ports and, their size
    output [11:0] bcd;
    //Internal variables
    reg [11 : 0] bcd; 
     reg [3:0] i;   
     
     //Always block - implement the Double Dabble algorithm
     always @(bin)
        begin
            bcd = 0; //initialize bcd to zero.
            for (= 0; i < 8; i = i+1) //run for 8 iterations
            begin
                bcd = {bcd[10:0],bin[7-i]}; //concatenation
                    
                //if a hex digit of 'bcd' is more than 4, add 3 to it.  
                if(< 7 && bcd[3:0] > 4) 
                    bcd[3:0] = bcd[3:0] + 3;
                if(< 7 && bcd[7:4] > 4)
                    bcd[7:4] = bcd[7:4] + 3;
                if(< 7 && bcd[11:8] > 4)
                    bcd[11:8] = bcd[11:8] + 3;  
            end
        end     
                
endmodule

Testbench Code:

module tb_bin2bcd;

    // Input
    reg [7:0] bin;
    // Output
    wire [11:0] bcd;
    // Extra variables
    reg [8:0] i;

    // Instantiate the Unit Under Test (UUT)
    bin2bcd uut (
        .bin(bin), 
        .bcd(bcd)
    );

//Simulation - Apply inputs
    initial begin
    //A for loop for checking all the input combinations.
        for(i=0;i<256;i=i+1)
        begin
            bin = i; 
            #10; //wait for 10 ns.
        end 
        $finish; //system function for stoping the simulation.
    end
      
endmodule

Simulation Waveform:

The code was synthesised and simulated using Xilinx ISE 13.1. A part of the waveform looked like this:


Some sample inputs and the corresponding outputs are shown below:

bin = "01100011" , output = "0000 1001 1001" (99).
bin = "11111110" , output = "0010 0101 0100" (254).
bin = "10111011" , output = "0001 1000 0111" (187).

Note :- The code can be modified to convert any length binary number to BCD digits.This require only very little change in the code.

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