In this post, I want to share Verilog code for a simple Digital clock. The module has two inputs - A Clock at 1 Hz frequency and an active high reset. There are three outputs to tell the time - seconds,minutes and hours.
The time units are incremented in an always block using Behavioral modelling. At every clock cycle we increment 'seconds'.Whenever seconds reaches the value '60' we increment 'minutes' by 1.Similarly whenever minutes reach '60' we increment 'hours' by 1.Once hours reaches the value '23' we reset the digital clock. The Verilog code for digital clock is given below:
Digital Clock:
module Digital_Clock(
Clk_1sec, //Clock with 1 Hz frequency
reset, //active high reset
seconds,
minutes,
hours);
//What are the Inputs?
input Clk_1sec;
input reset;
//What are the Outputs?
output [5:0] seconds;
output [5:0] minutes;
output [4:0] hours;
//Internal variables.
reg [5:0] seconds;
reg [5:0] minutes;
reg [4:0] hours;
//Execute the always blocks when the Clock or reset inputs are
//changing from 0 to 1(positive edge of the signal)
always @(posedge(Clk_1sec) or posedge(reset))
begin
if(reset == 1'b1) begin //check for active high reset.
//reset the time.
seconds = 0;
minutes = 0;
hours = 0; end
else if(Clk_1sec == 1'b1) begin //at the beginning of each second
seconds = seconds + 1; //increment sec
if(seconds == 60) begin //check for max value of sec
seconds = 0; //reset seconds
minutes = minutes + 1; //increment minutes
if(minutes == 60) begin //check for max value of min
minutes = 0; //reset minutes
hours = hours + 1; //increment hours
if(hours == 24) begin //check for max value of hours
hours = 0; //reset hours
end
end
end
end
end
endmodule
Testbench for Digital Clock:
module tb_clock;
// Inputs
reg Clk_1sec;
reg reset;
// Outputs
wire [5:0] seconds;
wire [5:0] minutes;
wire [4:0] hours;
// Instantiate the Unit Under Test (UUT)
Digital_Clock uut (
.Clk_1sec(Clk_1sec),
.reset(reset),
.seconds(seconds),
.minutes(minutes),
.hours(hours)
);
//Generating the Clock with `1 Hz frequency
initial Clk_1sec = 0;
always #50000000 Clk_1sec = ~Clk_1sec; //Every 0.5 sec toggle the clock.
initial begin
reset = 1;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
end
endmodule
Simulation Waveform:
The code was simulated using Xilinx ISE 13.1. The waveform is long, and it's not possible to post the whole waveform here. I have shown two relevant sections in the waveform.
The time units are incremented in an always block using Behavioral modelling. At every clock cycle we increment 'seconds'.Whenever seconds reaches the value '60' we increment 'minutes' by 1.Similarly whenever minutes reach '60' we increment 'hours' by 1.Once hours reaches the value '23' we reset the digital clock. The Verilog code for digital clock is given below:
Digital Clock:
module Digital_Clock(
Clk_1sec, //Clock with 1 Hz frequency
reset, //active high reset
seconds,
minutes,
hours);
//What are the Inputs?
input Clk_1sec;
input reset;
//What are the Outputs?
output [5:0] seconds;
output [5:0] minutes;
output [4:0] hours;
//Internal variables.
reg [5:0] seconds;
reg [5:0] minutes;
reg [4:0] hours;
//Execute the always blocks when the Clock or reset inputs are
//changing from 0 to 1(positive edge of the signal)
always @(posedge(Clk_1sec) or posedge(reset))
begin
if(reset == 1'b1) begin //check for active high reset.
//reset the time.
seconds = 0;
minutes = 0;
hours = 0; end
else if(Clk_1sec == 1'b1) begin //at the beginning of each second
seconds = seconds + 1; //increment sec
if(seconds == 60) begin //check for max value of sec
seconds = 0; //reset seconds
minutes = minutes + 1; //increment minutes
if(minutes == 60) begin //check for max value of min
minutes = 0; //reset minutes
hours = hours + 1; //increment hours
if(hours == 24) begin //check for max value of hours
hours = 0; //reset hours
end
end
end
end
end
endmodule
Testbench for Digital Clock:
module tb_clock;
// Inputs
reg Clk_1sec;
reg reset;
// Outputs
wire [5:0] seconds;
wire [5:0] minutes;
wire [4:0] hours;
// Instantiate the Unit Under Test (UUT)
Digital_Clock uut (
.Clk_1sec(Clk_1sec),
.reset(reset),
.seconds(seconds),
.minutes(minutes),
.hours(hours)
);
//Generating the Clock with `1 Hz frequency
initial Clk_1sec = 0;
always #50000000 Clk_1sec = ~Clk_1sec; //Every 0.5 sec toggle the clock.
initial begin
reset = 1;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
end
endmodule
Simulation Waveform:
The code was simulated using Xilinx ISE 13.1. The waveform is long, and it's not possible to post the whole waveform here. I have shown two relevant sections in the waveform.
sequential using non-blocking
ReplyDeleteThis code won't compile for sure since you aren't running through non-blocking statements
ReplyDeletecan you explain why we are using 6 registers for minutes and seconds, while we are using 5 registers for hours??
ReplyDeletesince there 60 minutes we require 6 bits i,e 6 registers to store and similarly seconds. where as there are 24 hours we require 5 bits to represent so we need 5 registers...
DeleteWe can represent 60 in minimum 6 bits and 24 in minimum 5 bits so ,that's why we use it here ..
Deletehow we can display it using 7 segment display with altera board has 6 of 7 segment display?
ReplyDeleteCan u explain sir plz
Deletemy clock is running very fastly in vivado 2017.4 version.Help me.
ReplyDeleteWhy the delay is 5000000 clk
ReplyDeletesir this code is giving me warning and showing a straight waveform please help?
ReplyDeletewarnings are:
clock and clock enable of counter are driven by the same logic
clock of seems to be used in the dATA or control logic of that element
It's showing seconds up to 45 only and 0 minutes and 0 hours
ReplyDeletehow we can display millisecond also?
ReplyDelete