Verilog Coding Tips and Tricks: Verilog Code for Ripple Carry Adder using Structural Level

Wednesday, October 21, 2015

Verilog Code for Ripple Carry Adder using Structural Level

Ripple carry adder(RCA) is the most basic form of digital adder for adding multi bit numbers. The adder is implemented by concatenating N full-adders to form a N-bit adder. For a 4 bit RCA, the block diagram can be drawn like this:

I have used the full adder and half adder modules written in a previous post to implement RCA. The coding is done in structural modelling. 

The code size can be much smaller and compact looking, if we use behavioral modelling. At the end of this post I have given a small snippet to give you an idea, of how.

4 bit Ripple Carry Adder:

//Verilog module for Ripple Carry Adder
module RC_adder(

//What are the Inputs?
    input [3:0] A;  
    input [3:0] B;
    input C_in;
//What are the Outputs? 
    output [3:0] Sum_out;
    output C_out;
//Internal variables.
    wire [3:0] Sum;
    wire [3:0] Carry;
    wire [3:0] Sum_out; 
    wire C_out;
    //Instantiate Full Adder 1
   full_adder fa1(
    .Data_in_A  (A[0]), 
    .Data_in_B  (B[0]), 
    .Data_in_C  (C_in),  
     .Data_out_Sum  (Sum[0]),
     .Data_out_Carry (Carry[0])

    //Instantiate Full Adder 2   
     full_adder fa2(
    .Data_in_A  (A[1]), 
    .Data_in_B  (B[1]), 
    .Data_in_C  (Carry[0]),  
     .Data_out_Sum  (Sum[1]),
     .Data_out_Carry (Carry[1])

    //Instantiate Full Adder 3   
     full_adder fa3(
    .Data_in_A  (A[2]), 
    .Data_in_B  (B[2]), 
    .Data_in_C  (Carry[1]),  
     .Data_out_Sum  (Sum[2]),
     .Data_out_Carry (Carry[2])

    //Instantiate Full Adder 4   
     full_adder fa4(
    .Data_in_A  (A[3]), 
    .Data_in_B  (B[3]), 
    .Data_in_C  (Carry[2]),  
     .Data_out_Sum  (Sum[3]),
     .Data_out_Carry (Carry[3])
     //Assign the final outputs.
     assign Sum_out = Sum;
     assign C_out = Carry[3];

Testbench for RCA:

module tb_RCA;

    // Inputs
    reg [3:0] A;
    reg [3:0] B;
    reg C_in;

    // Outputs
    wire [3:0] Sum_out;
    wire C_out;

    // Instantiate the Unit Under Test (UUT)
    RC_adder uut (

    initial begin
        //Apply Inputs
        A = 3;      B = 6;      C_in = 0;       #100;
        A = 5;      B = 7;      C_in = 1;       #100;
        A = 6;      B = 4;      C_in = 0;       #100;
        A = 8;      B = 9;      C_in = 1;       #100;
        A = 11;     B = 10;     C_in = 0;       #100;
        A = 13;     B = 11;     C_in = 1;       #100;
        A = 15;     B = 3;      C_in = 0;       #100;
        A = 0;      B = 0;      C_in = 1;       #100;

Simulation Waveform:

The codes, when properly simulated will give you the following waveform in Xilinx ISE 131.

Behavioral Modelling:

As I mentioned before, the code when written using behavioral modelling will look much more compact. I am not sharing the whole code here, I will leave it to you as an exercise.

But the crucial statement would look like this,

assign {C_out,Sum_out} = A+B+C_in;

 Where C_out and Sum_out are declared as wire's.
{ } are used for concatenation. 
'+' is an operator defined in Verilog for addition.

1 comment:

  1. vipin bro in need the code of carry save,carry skip nd carry look ahead can u post those three codes for me plz...